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1 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD80800 data sheet: ACD80800 re v .1.0.0. e last update: s ep te mb er 19 , 2 00 0 acd confidential material for acd authorized customer use only. no reproduction or redistribution without acds prior permission. address resolution logic (8k mac addresses) advanced communication devices please check acds website for update information before starting a design w eb site: http://www .acdcorp.com/tech.html or contact acd at: email: support@acdcorp.com t el: 510- 35 4 - 68 10 fax: 510- 35 4 -6 8 34
2 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD80800 content list 1. summary 2. features 3. functional description 4. pin description 5. interface description 6. register description 7. command description 8. timing description 9. electrical specification 10. packaging
3 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD80800 1. summary the ACD80800 serves as an address resolution logic for acds switch controller chips (acd82124, acd82012 etc.) through a glueless arl interface. it automatically builds up an address table and can map up to 8k mac addresses into their associated ports. the ACD80800 can work without a cpu in a unmanaged switch system, or with a cpu and an acd mib (acd80900 management information base). a direct input/output interface is integrated to support a man- agement cpu. the cpu can configure the operation mode of the ACD80800, learn all the addresses in the address table, add new addresses into the table, con- trol security or filtering features of each address entry, etc. the ACD80800 is designed with such a high perfor- mance that, it will never slow down the frame switching operation conducted by the acds switch controllers. together with the non-blocking architecture of the acds switch controllers, the chip set (a acd switch controller plus the ACD80800, plus acd80900 in a managed switch system) can provide wire speed forwarding rate under any type of traffic load. 2. features supports up to 8k mac address lookup provides glueless arl interface with acds switch controller chip provides direct input/output type of interface for the management cpu provides uart type of interface for the manage- ment cpu wire speed address lookup time. wire speed address learning time. address can be automatically learned from switch without the cpu intervention address can be manually added by the cpu through the cpu interface each mac address can be secured by the cpu from being changed or aged out each mac address can be marked by the cpu from receiving any frame each newly learned mac address is notified to the cpu each aged out mac address is notified to the cpu automatic address aging control, with configurable aging period 0.35 micron, 3.3v cmos technology 128-pin pqfp package acd82xxx n-port fast ethernet switch controller asram ACD80800 address resolution logic acd80900 mib cpu p(n-1) p1 p0 figure-1: ACD80800 used in a managed n-port fast ethernet switch system p(n-3) p(n-2)
4 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD80800 cpu interface address registers data registers command registers control registers switch interface address learning engine cpu interface engine address table (8k entries) figure-2. ACD80800 block diagram address aging engine address lookup engine 3. functional description ACD80800 provides address resolution service for acds switch controller chip. ACD80800 provides a glueless interface with acds switch controller, and is used to build an address table and provide address lookup service to acds switch controller. figure 2 is a block diagram of ACD80800. t raf fic snooping all ethernet frames received by acds switch controller have to be stored into memory buffer. as the frame data are written into memory, the status of the data shown on the data bus are displayed by acds switch controller through a state bus. ACD80800s switch con- troller interface contains the signals of the data bus and the state bus. by snooping the data bus and the state bus of acds switch controller, ACD80800 can detect the occurrence of any destination mac address and source mac address embedded inside each frame. address learning each source address caught from the data bus, to- gether with the id of the ingress port, is passed to the address learning engine of ACD80800. the address learning engine will first determine whether the frame is a valid frame. for a valid frame, it will first try to find the source address from the current address table. if that address doesnt exist, or if it does exist but the port id associated with the mac address is not the ingress port, the address will be learned into the address table. after an address is learned by the address learning engine, the cpu will be notified to read this newly learned address so that it can add it into the cpus address table. address aging after each source address is learned into the address table, it has to be refreshed at least once within each address aging period. refresh means it is caught again from the switch interface. if it has not occurred for a pre-set aging period, the address aging engine will re- move the address from the address table. after an ad- dress is removed by the address aging engine, the cpu will be notified through interrupt request that it needs to read this aged out address so that it can remove this address from the cpus address table. address lookup each destination address is passed to the address
5 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD80800 lookup engine of ACD80800. the address lookup engine checks if the destination address matches with any existing address in the address table. if it does, ACD80800 returns the associated port id to acds switch controller through the output data bus. other- wise, a no match result is passed to acds switch con- troller through the output data bus. cpu interface ACD80800 provides a direct input/output type of inter- face for a management cpu to access various kind of registers inside ACD80800. the interface has 8-bit data bus, and 5-bit address bus. the timing of read and write operation is controlled by output enable signal and write enable signal. for details of cpu interface timing information, refer to the section of timing descrip- tion. the cpu can also choose to access the registers of ACD80800 by sending commands to the uart data input line. each command is consisted by action (read or write), register type, register index, and data. each result of command execution is returned to the cpu through the uart data output line. cpu interface registers ACD80800 provides a bunch of registers for the control cpu. through the registers, the cpu can read all ad- dress entries of the address table, delete particular ad- dresses from the table, add particular addresses into the table, secure an address from being changed, set filtering on some addresses, change the hashing algo- rithm etc. through a proper interrupt request signal, the cpu can be notified whenever it needs to retrieve data for a newly-learned address or an aged-out address so that the cpu can build an exact same address table learned by ACD80800. cpu interface engine the command sent by the control cpu is executed by the cpu interface engine. for example, the cpu may send a command to learn the first newly-learned ad- dress. the cpu interface engine is responsible to find the newly-learned address from the address table, and passes it to cpu. the cpu may request to learn next newly-learned address. then, it is again the responsi- bility of the cpu interface engine to search for next newly-learned address from the address table. address t able the address table can hold up to 8k mac addresses, together with the associated port id, security flag, filter- ing flag, new flag, aging information etc. the address table resides in the embedded sram inside ACD80800.
6 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD80800 4. pin descriptions 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 128 125 126 127 124 121 122 123 120 117 118 119 116 113 114 115 112 109 110 111 108 105 106 107 104 103 39 42 41 40 43 45 44 48 47 46 49 52 51 50 53 56 55 54 57 60 59 58 61 64 63 62 gnd swdi63 swdi62 swdi61 swdi60 swdi59 swdi58 swdi57 swdi56 swdi55 swdi54 swdi53 swdi52 swdi51 swdi50 swdi49 swdi48 vdd gnd swdi47 swdi46 swdi45 swdi44 swdi43 swdi42 swdi41 swdi40 vdd gnd swdi39 gnd vdd swdi0 swdi1 swdi2 swdi3 swdi4 swdi5 vdd gnd nreset vdd swdi24 swdi26 swdi25 swdi28 swdi38 swdi29 swdi27 swdi19 swdi20 swdi7 swdi8 swdi22 swdi23 swdi21 swdi13 swdi14 swdi16 swdi15 swdi18 vdd swdi17 swdi10 swdi12 swdi11 swdi9 gnd figure-3: pin diagram of ACD80800 (the arl chip) swdo0 swdo1 swdov swdo3 swdo2 33 34 35 36 37 38 swdi37 swdi36 swdi35 swdi34 swdi33 swdi32 101 102 100 97 98 99 swdi31 swdi30 swdi6 gnd vdd vdd gnd swstat0 sweof swstat3 swpid1 swpid2 swpid4 swpid3 swsync gnd vdd swstat2 swstat1 swdir0 swclk swpid0 uartdo uartdi swdir1 cpud7 cpud6 cpud5 cpud4 cpud3 cpud2 cpud1 cpud0 gnd vdd ncpuoe ncpucs cpua0 ncpuwe cpua1 cpua2 cpua3 cpua4 gnd gnd wchdog cpuirq gnd nc
7 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD80800 pin table pin name description i/o pin name description i/o 1gnd ground. - 65 gnd gr ound. - 2 s wdi63 data from switch controller chip. 3.3v i 66 s wdi5 data from switch controller chip. 3.3v i 3 s wdi62 data from switch controller chip. 3.3v i 67 s wdi4 data from switch controller chip. 3.3v i 4 s wdi61 data from switch controller chip. 3.3v i 68 s wdi3 data from switch controller chip. 3.3v i 5 s wdi60 data from switch controller chip. 3.3v i 69 s wdi2 data from switch controller chip. 3.3v i 6 s wdi59 data from switch controller chip. 3.3v i 70 s wdi1 data from switch controller chip. 3.3v i 7 s wdi58 data from switch controller chip. 3.3v i 71 s wdi0 data from switch controller chip. 3.3v i 8 s wdi57 data from switch controller chip. 3.3v i 72 vdd 3.3v power s upply. - 9 s wdi56 data from switch controller chip. 3.3v i 73 gnd gr ound. - 10 s wdi55 data from switch controller chip. 3.3v i 74 s wdov output data valid s ignal to s witch controller chip. 3.3v o 11 s wdi54 data from switch controller chip. 3.3v i 75 s wdo3 output data to switch controller chip. 3.3v o 12 s wdi53 data from switch controller chip. 3.3v i 76 s wdo2 output data to switch controller chip. 3.3v o 13 s wdi52 data from switch controller chip. 3.3v i 77 s wdo1 output data to switch controller chip. 3.3v o 14 s wdi51 data from switch controller chip. 3.3v i 78 s wdo0 output data to switch controller chip. 3.3v o 15 s wdi50 data from switch controller chip. 3.3v i 79 vdd 3.3v power s upply. 3.3v - 16 s wdi49 data from switch controller chip. 3.3v i 80 gnd gr ound. - 17 s wdi48 data from switch controller chip. 3.3v i 81 gnd gr ound. - 18 vdd 3.3v power s uppl y. - 82 s w cl k 50mh z r ef er en ce cl ock s i gn al f r om s wi tch con tr ol l er ch i p. 3. 3v i 19 gnd ground. - 83 s wpid0 port id indication signal from switch controller chip. 3.3v i 20 s wdi47 data from switch controller chip. 3.3v i 84 s wpid1 port id indication signal from switch controller chip. 3.3v i 21 s wdi46 data from switch controller chip. 3.3v i 85 s wpid2 port id indication signal from switch controller chip. 3.3v i 22 s wdi45 data from switch controller chip. 3.3v i 86 s wpid3 port id indication signal from switch controller chip. 3.3v i 23 s wdi44 data from switch controller chip. 3.3v i 87 s wpid4 port id indication signal from switch controller chip. 3.3v i 24 s wdi43 data from switch controller chip. 3.3v i 88 s ws ync port 0 indication signal from switch controller chip. 3.3v i 25 s wdi42 data from switch controller chip. 3.3v i 89 s we of e nd of f rame indication s ignal from s witch controller chip. 3.3v i 26 s wdi41 data from switch controller chip. 3.3v i 90 vdd 3.3v power s upply. - 27 s wdi40 data from switch controller chip. 3.3v i 91 gnd gr ound. - 28 s wdi39 data from switch controller chip. 3.3v i 92 s w s t a t 0 d at a s tatu s s i g n al f r om s wi tch con tr ol l er ch i p . 3 . 3 v i 29 s wdi38 data from switch controller chip. 3.3v i 93 s w s t a t 1 d at a s tatu s s i g n al f r om s wi tch con tr ol l er ch i p . 3 . 3 v i 30 s wdi37 data from switch controller chip. 3.3v i 94 s w s t a t 2 d at a s tatu s s i g n al f r om s wi tch con tr ol l er ch i p . 3 . 3 v i 31 s wdi36 data from switch controller chip. 3.3v i 95 s w s t a t 3 d at a s tatu s s i g n al f r om s wi tch con tr ol l er ch i p . 3 . 3 v i 32 s wdi35 data from switch controller chip. 3.3v i 96 s wdir0 data direction indication signal from switch controller chip. 3.3v i 33 s wdi34 data from switch controller chip. 3.3v i 97 s wdir1 data direction indication signal from switch controller chip. 3.3v i 34 s wdi33 data from switch controller chip. 3.3v i 98 nc not connected. - 35 s wdi32 data from switch controller chip. 3.3v i 99 nre s e t hardware res et pin. 3.3v i 36 s wdi31 data from switch controller chip. 3.3v i 100 wchdog watch dog signal. 3.3v o 37 s wdi30 data from switch controller chip. 3.3v i 101 gnd gr ound. - 38 vdd 3.3v power s uppl y. - 102 vdd 3.3v power s upply. - 39 gnd ground. - 103 gnd gr ound. - 40 s wdi29 data from switch controller chip. 3.3v i 104 uart di uart data input line. 3.3v i 41 s wdi28 data from switch controller chip. 3.3v i 105 uart do uart data output line. 3.3v o 42 s wdi27 data from switch controller chip. 3.3v i 106 vdd 3.3v power s upply. - 43 s wdi26 data from switch controller chip. 3.3v i 107 gnd gr ound. - 44 s wdi25 data from switch controller chip. 3.3v i 108 cpuirq interrupt request. 3.3v o 45 s wdi24 data from switch controller chip. 3.3v i 109 cp ud0 cp u data bus . 3.3v i/ o 46 s wdi23 data from switch controller chip. 3.3v i 110 cp ud1 cp u data bus . 3.3v i/ o 47 s wdi22 data from switch controller chip. 3.3v i 111 cp ud2 cp u data bus . 3.3v i/ o 48 s wdi21 data from switch controller chip. 3.3v i 112 cp ud3 cp u data bus . 3.3v i/ o 49 s wdi20 data from switch controller chip. 3.3v i 113 cp ud4 cp u data bus . 3.3v i/ o 50 s wdi19 data from switch controller chip. 3.3v i 114 cp ud5 cp u data bus . 3.3v i/ o 51 s wdi18 data from switch controller chip. 3.3v i 115 cp ud6 cp u data bus . 3.3v i/ o 52 s wdi17 data from switch controller chip. 3.3v i 116 cp ud7 cp u data bus . 3.3v i/ o 53 s wdi16 data from switch controller chip. 3.3v i 117 vdd 3.3v power s upply. - 54 s wdi15 data from switch controller chip. 3.3v i 118 gnd gr ound. - 55 s wdi14 data from switch controller chip. 3.3v i 119 cpua0 cpu address bus. 3.3v i 56 s wdi13 data from switch controller chip. 3.3v i 120 cpua1 cpu address bus. 3.3v i 57 s wdi12 data from switch controller chip. 3.3v i 121 cpua2 cpu address bus. 3.3v i 58 s wdi11 data from switch controller chip. 3.3v i 122 cpua3 cpu address bus. 3.3v i 59 s wdi10 data from switch controller chip. 3.3v i 123 cpua4 cpu address bus. 3.3v i 60 s wdi9 data from switch controller chip. 3.3v i 124 ncp u oe ou tput e nabl e s i gnal f r om cp u . 3.3v i 61 s wdi8 data from switch controller chip. 3.3v i 125 ncp uwe write e nable s ignal from cp u. 3.3v i 62 s wdi7 data from switch controller chip. 3.3v i 126 ncp ucs chip s elect s ignal from cp u. 3.3v i 63 s wdi6 data from switch controller chip. 3.3v i 127 gnd gr ound. - 64 vdd 3.3v power s uppl y. - 128 vdd 3.3v power s upply. -
8 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD80800 table-1: switch interface name type description swdi0 ~ swdi63 i input data, which can be 48- bit or 64-bit wide swstat0 ~ swstat3 i input data state sweof i end of frame indication signal swdir0 ~ swdir1 i data direction indication signal swsync i port synchronization signal swpid0 ~ swpid4 i port-id indication signal swclk i reference clock swdov o output data valid signal swdo0 ~ swdo3 o output data which can be 2- bit or 4-bit wide 5. interface description switch interface switch interface provides a communication channel between acds switch controller chip and ACD80800. as a frame is being received by acds switch control- ler chip , the destination address and source address of the frame are snooped from the swdix lines of ACD80800, with respect to the swclk signal. ACD80800 carries a lookup process for each destina- tion address, and a learning process for each source address. the result of the lookup is returned to the switch controller chip through the swdox lines. table 1 shows the associated signals in the switch interface. the swdix signal comes from the sram data bus of acds switch controller chip . since all data of the re- ceived frames have to be written into the shared memory through the data bus, the bus can be monitored for occurrence of da and sa values, indicated by the as- sociated state bits. the signals in swdix bus can be a 48-bit or 64-bit wide data bus. for a 48-bit wide bus, the first word will be the da and the second word will be the sa. for a 64-bit wide bus, da is the first 48-bit of first word, sa is the last 16-bit of first word plus first 32- bit of second word. swdir is a 2-bit signal to indicate the direction of the data displayed on the swdi bus, 01 for receiving, 10 for transmitting, 00 or 11 for other states. ACD80800 only deals with the received data. swstat bus is a 4-bit signal, used to indicate the mean- ing (status) of the data. the 4-bit status is defined as: 0000 - third to last word 0001 - first word 0010 - second word 0011 - reserved 0100 - reserved 0101 - drop event 0110 - jabber 0111 - false carrier 1000 - alignment error 1001 - flow control/collision * 1010 - short event/excessive collision * 1011 - runt/late collision * 1100 - symbol error 1101 - fcs error 1110 - long event 1111 - reserved * note: error type depends on swdir is 01 or 10. swsync is used to indicate port 0 is driving the data bus. it is used when the bus is evenly allocated in a time division multiplexing manner, such that a monitoring de- vice can implement a counter to indicate the id of the port which is driving the swdi bus, and use swsync signal to reset the counter. when swsync is in use, swpid is ignored. swpid is used to indicate the id of the port which is driving the data bus. when swpid is in use, swsync is ignored. sweof is used to indicate the start and end of a frame. it is always asserted when the corresponding port is idling. the start of a frame is indicated by a high-to-low transition of sweof signal. the end of a frame is indi- cated by a low to high transition of sweof signal. swclk is used to provide timing reference of input data snooping and output data latching. the signal is also used as the system clock of the chip. swdov is used to indicate the start of a lookup result package. swdox is used to return the result of lookup to acds switch controller chip. data is latched onto swdox bus with respect to the rising edge of swclk signal. each result package is consisted by 5-bit source port id, 2- bit result, and 5-bit destination port id. the 2-bit result field is defined as 01 for match, with the port id shown by the 5-bit destination port id field; 10 for no match; 11 for forced disregard (filtering).
9 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD80800 table-2: cpu interface name i/o description cpua0 ~ cpua4 i 5 address lines for register selection. cpud0 ~ cpud7 i/o 8 data lines. ncpuoe i read enable signal, low active. ncpuwe i write enable signal, low active. ncpucs i chip select signal, low active. cpuirq o interrupt request signal. uartdi i uart input data line. uartdo o uart output data line. header address data checksum header address data checksum table-3: other interface name i/o description wchdog o alive signal from ACD80800 to indicate it is working properly. nreset i hardware reset si gnal, low active. vdd - 3.3v power supply. gnd - ground. cpu interface the cpu interface provides a communication channel between the cpu and the ACD80800. basically, the cpu sends command to the ACD80800 by writing into associated registers, and retrieve result from ACD80800 by reading corresponding registers. the registers are described in the section of register description. the cpu interface signals are described by table 2 : cpuax is the address bus used to select the registers of the ACD80800. cpudx is the data bus used to pass data between the cpu and the registers of the ACD80800. ncpuoe is used to control the timing of the read op- eration. ncpuwe is used to control the timing of the write op- eration. ncpucs is used to make the ACD80800 active to the ncpuoe or ncpuwe signals. cpuirq is used to generate an interrupt request to the cpu. for each source of the interrupt, refer to the de- scription of the interrupt source register. uartdi is used by the control cpu to send command into the ACD80800. the baud rate will be automatically detected by the ACD80800. the result will be returned through the uartdo line with the detected baud rate. the format of the command packet is shown as follows: where: header is further defined as: * b1:b0 - read or write, 01 for read, 11 for write * b4:b2 - device number, 000 to 111 (0 to 7) * b7:b5 - device type, 010 for arl address - 8-bit value used to select the reg- ister to access data - 32-bit value, only the lsb is used for write operation, all 0 for read operation checksum - 8-bit value of xor of all bytes uartdo is used to return the result of command ex- ecution to the cpu. the format of the result packet is shown as follows: where: header is further defined as: * b1:b0 - read or write, 01 for read, 11 for write * b4:b2 - device number, 000 to 111 (0 to 7) * b7:b5 - device type, 010 for arl address - 8-bit value for address of the selected register data - 32-bit value, only the lsb is used for read operation, all 0 for write operation checksum - 8-bit value of xor of all bytes the ACD80800 will always check the cmd header to see if both the device type and the device number matches with its setting. if not, it ignores the command and will not generate any response to this command. other interface (table 3) wchdog signal is used to prevent the system from hitting dead-lock by any abnormal event. under normal condition, the output signal from the wchdog pin will not stay at low for longer than 10ms. if the state of
10 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD80800 table-4: register description reg. name description 0 datareg0 byte 0 of data 1 datareg1 byte 1 of data 2 datareg2 byte 2 of data 3 datareg3 byte 3 of data 4 datareg4 byte 4 of data 5 datareg5 byte 5 of data 6 datareg6 byte 6 of data 7 datareg7 byte 7 of data 8 addrreg0 lsb of address value 9 addrreg1 msb of address value 10 cmdreg command register 11 rsltreg result register 12 cfgreg configuration register 13 intsrcreg interrupt source register 14 intmskreg interrupt mask register 15 nlearnreg0 address learning disable register for port 0 - 7 16 nlearnreg1 address learning disable register for port 8 - 15 17 nlearnreg2 address learning disable register for port 16 - 23 18 agetimereg0 lsb of aging period register 19 agetimereg 1 msb of aging period register 20 poscfg0 power on strobe configuration register 0 21 poscfg1 power on strobe configuration register 1 wchdog remains at low state, the chip is not working properly and needs to be reset. nreset pin is used to do a hardware reset to the ACD80800. please note that after a hardware reset, all learned address is cleared, and the address table has to be built again. configuration interface the following table shows the power-on-strobed con- figuration setting: into the command register. when a new command is written into the command register, ACD80800 will change the status of the result register to 0. the result register will indicate the completion of the command at the end of the execution. before the completion of the execution, any command written into the command register is ignored by ACD80800. the registers accessible to the cpu are described by table 4 : the dataregx are registers used to pass the param- eter of the command to the ACD80800, and the result of the command to the cpu. the addrregx are registers used to specify the address associated with the command. the cmdreg is used to pass the type of command to the ACD80800. the command types are listed in table 5 . the details of each command is described in the chapter of command description. power-on-strobed setting name description shared pin# bist enable boot-internal-self-test for optional internal ram test 78 ic test enable ic manufacturer test use only: always pull low 77 dio enable 1 = data i/o 76 0 = uart mode port id select 1 = for 82124 or 82012 75 0 = reserved no cpu 11 = no cpu, 80800 will self initiate 74/111 00 = with cpu, 80800 will wait for cpu to initiate bus width selection 00 = 32 bit ( reserved ) 110/109 01 = 48 bit ( 82124 or 82012) 10 = reserved 11 = 64 bit ( reserved ) uart id 000 = id for the only or the first 80800 on the system 114/113/112 001 = id for the second 80800 on the system with two 80800s note: high=1=enable 6. register description ACD80800 provides a bunch of registers for the cpu to access the address table inside it. command is sent to ACD80800 by writing into the associated registers. before the cpu can pass a command to ACD80800, it must check the result register (register 11) to see if the command has been done. when the result register indicates the command has been done, the cpu may need to retrieve the result of previous command first. after that, the cpu has to write the associated parameter of the command into the data registers. then, the cpu can write the command type
11 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD80800 table-5: command list command description 0x09 add the specified mac address into the address table 0x0a set a lock for the specified mac address 0x0b set a filtering flag for the specified mac address 0x0c delete the specified mac address from the address table 0x0d assign a port id to the specified mac address 0x10 read the first entry of the address table 0x11 read next entry of address book 0x20 read first valid entry 0x21 read next valid entry 0x30 read first new page 0x31 read next new page 0x40 read first aged page 0x41 read next aged page 0x50 read first locked page 0x51 read next locked page 0x60 read first filtered page 0x61 read next filtered page 0x80 read first page with specified pid 0x81 read next page with specified pid 0xff system reset the rstreg is used to indicate the status of command execution. the result code is listed as follows: 01 - command is being executed and is not done yet 10 - command is done with no error 1x - command is done, with error indi- cated by x, where x is a 4-bit error code: 0001 for cannot find the entry as speci- fied the cfgreg is used to configure the way the ACD80800 works. the bit definition of cfgreg is described as: bit 0 - disable address aging bit 1 - disable address lookup bit 2 - disable da cache bit 3 - disable sa cache bit 7:4 - hashing algorithm selection, default is 0000 the intsrcreg is used to indicate what can cause interrupt request to cpu. the source of interrupt is listed as: bit 0 - aged address exists bit 1 - new address exists bit 2 - reserved bit 3 - reserved bit 4 - bucket overflowed bit 5 - command is done bit 6 - system initialization is completed bit 7 - self test failure the intmskreg is used to enable an interrupt source to generate an interrupt request. the bit definition is the same as intsrcreg. a 1 in a bit enables the corresponding interrupt source to generate an interrupt request once it is set. the nlearnreg[2:0] are used to disable address learning activity from a particular port. if the bit corresponding to a port is set, ACD80800 will not try to learn new addresses from that port. the agetimereg[1:0] are used to specify the period of address aging control. the aging period can be from 0 to 65535 units, with each unit counted as 2.684 second. the poscfgreg0 is a configuration register whose default value is determined by the pull-up or pull-down status of the associated hardware pin. the bits of poscfgreg0 is listed as follows: bit 0 - bisten, shared with arldo0, 0 for no self test, 1 for enable self test bit 1 - testen, shared with arldo1, 0 for normal operation, 1 for production test. bit 2 - dioen, shared with arldo2, 0 for using uart, 1 for using dio. bit 3 - syncen, shared with arldo3, 0 for using swpid, 1 for using swsync. bit 4 - nocpu * , 0 for have a control cpu, 1 for do not have a control cpu. note: when nocpu is set as 0, ACD80800 will not start the initialization process until a system start command is sent to the command register. the poscfgreg1 is a configuration register whose default value is determined by the pull-up or pull-down status of the associated hardware pin. the bits of poscfgreg1 is listed as follows: bit 1:0 - busmode, shared with cpud1:cpud0, bus width selection, 01 for 48-bit, 10 for 64 bit. bit 2 - cpugo, shared with cpud2, only effective when nocpu bit of poscfgreg0 is set to 1. setting cpugo to 0 means
12 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD80800 b7 b6 b5 b4 b3 b2 b1 b0 rsvd rsvd filter lock new old age valid wait for the cpu to send the system start command before the initialization process can be started. bit 5:3 - uartid, shared with cpud5:cpud3, 3-bit id for uart communication. 7. command description command 09h description: add the specified mac address into the address table. parameter: store the mac address into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. store the associated port number into datareg6. result: the mac address will be stored into the address table if there is space available. the result is indicated by the result register. command 0ah description: set the lock bit for the specified mac address. parameter: store the mac address into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. result: the state machine will seek for an entry with matched mac address, and set the lock bit of the entry. the result is indicated by the result register. command 0bh description: set the filter flag for the specified mac address. parameter: store the mac address into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. result: the state machine will seek for an entry with matched mac address, and set the filter bit of the entry. the result is indicated by the result register. command 0ch description: delete the specified mac address from the address table. parameter: store the mac address into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. result: the mac address will be removed from the address table. the result is indicated by the result register. command 0dh description: assign the associated port number to the specified mac address. parameter: store the mac address into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. store the port number into datareg6. result: the port id field of the entry containing the specified mac address will be changed accordingly. the result is indicated by the result register. command 10h description: read the first entry of the address table. parameter: none result: the result is indicated by the result register. if the command is completed with no error, the content of the first entry of the address book will be stored into the data registers. the mac address will be stored into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag * bits are stored in datareg7.the read pointer will be set to point to second entry of the address book. note - the flag bits are defined as: where: filter - 1 indicates the frame heading to this address should be dropped. lock - 1 indicates the entry should never be changed or aged out. new - 1 indicates the entry is a newly learned address. old - 1 indicates the address has been aged out. age - 1 indicates the address has not
13 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD80800 been visited for current age cycle. valid - 1 indicates the entry is a valid one. rsvd - reserved bits. command 1 1h description: read next entry of address book. parameter: none result: the result is indicated by the result register. if the command is completed with no error, the content of the address book entry pointed by read pointer will be stored into the data registers. the mac address will be stored into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag bits are stored in datareg7. the read pointer will be increased by one. command 20h description: read first valid entry. parameter: none result: the result is indicated by the result register. if the command is completed with no error, the content of first valid entry of the address book will be stored into the data registers. the mac address will be stored into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag bits are stored in datareg7. the read pointer is set to point to this entry. command 21h description: read next valid entry. parameter: none result: the result is indicated by the result register. if the command is completed with no error, the content of next valid entry from the read pointer of the address book will be stored into the data registers. the mac address will be stored into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag bits are stored in datareg7. the read pointer is set to point to this entry. command 30h description: read first new page. parameter: none result: the result is indicated by the result register. if the command is completed with no error, the content of first new entry of the address book will be stored into the data registers. the mac address will be stored into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag bits are stored in datareg7. the read pointer is set to point to this entry. command 31h description: read next new entry. parameter: none result: the result is indicated by the result register. if the command is completed with no error, the content of next new entry from the read pointer of the address book will be stored into the data registers. the mac address will be stored into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag bits are stored in datareg7. the read pointer is set to point to this entry. command 40h description: read first aged entry. parameter: none result: the result is indicated by the result register. if the command is completed with no error, the content of first aged entry of the address book will be stored into the data registers. the mac address will be stored into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag bits are stored in datareg7. the read pointer is set to point to this entry. command 41h description: read next aged entry. parameter: none result: the result is indicated by the result register. if the command is completed with no error, the content of next aged entry from the read pointer of the address book will be stored into the data registers. the mac address will be stored into datareg5 - datareg0, with datareg5 contains the msb of the
14 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD80800 mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag bits are stored in datareg7. the read pointer is set to point to this entry. command 50h description: read first locked entry. parameter: none result: the result is indicated by the result register. if the command is completed with no error, the content of first locked entry of the address book will be stored into the data registers. the mac address will be stored into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag bits are stored in datareg7. the read pointer is set to point to this entry. command 51h description: read next locked entry. parameter: none result: the result is indicated by the result register. if the command is completed with no error, the content of next locked entry from the read pointer of the address book will be stored into the data registers. the mac address will be stored into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag bits are stored in datareg7. the read pointer is set to point to this entry. command 60h description: read first filtered page. parameter: none result: the result is indicated by the result register. if the command is completed with no error, the content of first filtered entry of the address book will be stored into the data registers. the mac address will be stored into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag bits are stored in datareg7. the read pointer is set to point to this entry. command 61h description: read next valid entry. parameter: none result: the result is indicated by the result register. if the command is completed with no error, the content of next filtered entry from the read pointer of the address book will be stored into the data registers. the mac address will be stored into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag bits are stored in datareg7. the read pointer is set to point to this entry. command 80h description: read first entry with specified port number. parameter: store port number into datareg6. result: the result is indicated by the result register. if the command is completed with no error, the content of first entry of the address book with the said port number will be stored into the data registers. the mac address will be stored into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag bits are stored in datareg7. the read pointer is set to point to this entry. command 81h description: read next valid entry. parameter: store port number into datareg6. result: the result is indicated by the result register. if the command is completed with no error, the content of next entry from the read pointer of the address book with the said port number will be stored into the data registers. the mac address will be stored into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag bits are stored in datareg7. the read pointer is set to point to this entry.
15 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD80800 command ffh description: system reset. parameter: none result: this command will reset the arl system. all entries of the address book will be cleared. b40 b47 b32 b39 b24 b31 b16 b23 b8 b15 b0 b7 frame bits b 4 7 b 4 6 b 4 1 b 4 2 b 4 3 b 4 4 b 4 5 x x d5 b 8 b 1 4 b 9 b 1 0 b 1 1 b 1 2 b 1 3 b 1 5 d4 b 1 6 b 2 2 b 1 7 b 1 8 b 1 9 b 2 0 b 2 1 b 2 3 d3 b 2 4 b 3 0 b 2 5 b 2 6 b 2 7 b 2 8 b 2 9 b 3 1 d2 b 3 2 b 3 8 b 3 3 b 3 4 b 3 5 b 3 6 b 3 7 b 3 9 d1 b 0 0 b 0 6 b 0 1 b 0 2 b 0 3 b 0 4 b 0 5 b 0 7 d0 b 0 b 6 b 1 b 2 b 3 b 4 b 5 b 7 figure-4: format of a 48-bit mac address in a data register note : the handling of the mac address is shown in figure 4 . special attention should be given to the location of bit 47 of the mac address, which is at bit 0 of d5 . the software needs to be aware of this and make the corresponding adjustment.
16 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD80800 t1 cpuax cpudx noe ncs t2 t3 valid data t4 t5 t7 t6 t9 t8 high-z high-z figure-5: timing of cpu read operation time description min typ max unit t1 read cycle time 50 - - ns t2 address access time 50 - - ns t3 output hold time 0 - - ns t4 noe access time - - 45 ns t5 nce access time - - 45 ns t6 noe to low-z output 0 - - ns t7 nce to low-z output 0 - - ns t8 noe to high-z output - - 5 ns t9 nce to high-z output - - 5 ns 8. timing descriptions
17 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD80800 t1 cpuax cpudx nce t2 t3 valid data t6 t9 t4 t8 t7 nwe t5 figure-6: timing of cpu write operation time description min typ max unit t1 write c y cle time 30 - - ns t2 address valid to write end 30 - - ns t3 address hold for write end 0 - - ns t4 nce to write end 25 - - ns t5 address setup time 0 - - ns t6 we pulse width 25 - - ns t7 data valid to write end 30 - - ns t8 data hold for write end 0 - - ns
18 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD80800 dc supply voltage : vdd -0.3v ~ +4.5v dc input current: iin +/-10 ma dc input voltage: vin -0.3 ~ vdd + 0.3v dc output voltage: vout -0.3 ~ vdd + 0.3v supply voltage: vdd 3.3v+/-10% operating temperature: ta 0 o c -70 o c maximum power dissipation 900mw 9. electrical specification absolute maximum ratings operation at absolute maximum ratings is not implied exposure to stresses outside those listed could cause permanent damage to the device. recommended operation conditions
19 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD80800 f l2 a2 a 1 r2 r1 l1 pqfp-128 a2 g e z d e1 e2 d1 d2 symble min nom max a1 0.25 0.33 na a2 2.57 2.71 2.87 d1 na 23.2 na d2 na 18.5 na ena0.5na e1 na 17.2 na e2 na 12.5 na f 0.13 0.15 0.17 g 0.13 0.2 0.28 l1 0.73 0.88 1.03 l2 na 1.6 na r1 0.13 na na r2 0.13 0.3 na z d na 0.75 na 10. packaging

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